1. Field of the Invention
This invention relates to a semiconductor device.
2. Description of Related Art
In recent years, vertical transistors have been proposed as a technique for transistor miniaturization.
The vertical transistor is a transistor which uses as a channel a semiconductor pillar extending in a direction perpendicular to a main surface of a semiconductor substrate.
Specifically, as disclosed in, for example, JP-A-2009-081389 (Patent Document 1), in a vertical transistor, a semiconductor pillar (base pillar) is provided to stand from a semiconductor substrate and a gate electrode is provided around the semiconductor pillar with a gate insulating film interposed therebetween. A drain region and a drain electrode are provided on the side of a lower portion of the semiconductor pillar while a source region and a source electrode are provided at an upper portion of the semiconductor pillar.
As compared with a conventional transistor in which a channel is disposed parallel to the substrate plane, the area in the plane occupied by the vertical transistor is smaller and, even if the channel length (gate length) is increased, there is no increase in transistor occupation area in the plane.
Consequently, it is possible to suppress the short channel effect without increasing the transistor occupation area in the plane. Further, the vertical transistor has an advantage that since the channel can be fully depleted, it is possible to obtain a satisfactory S value (subthreshold swing value) and a large drain current.
In addition, in the vertical transistor, since the gate electrode is formed over the entire periphery of the channel, i.e. the gate electrode covers the entire periphery of the channel, it is possible to effectively control the potential of the channel by a voltage applied to the gate electrode without being affected by external factors other than the source and the drain.